The present invention relates to a semiconductor memory device in which the memory cell array is made up from memory cells which are the same as a DRAM (dynamic random access memory), and moreover which, when seen from the outside of the semiconductor memory device, operates with the same specifications as a general-purpose SRAM (static RAM). In particular, the present invention relates to a semiconductor memory device which is suitable for incorporation into a portable instrument, as represented by a portable telephone or PHS (personal handyphone system) or the like.
SRAMs and DRAMs are typical representatives of semiconductor memory devices which are capable of random access. When compared with a DRAM, generally an SRAM is high speed, and if it is supplied with power source and merely an address is input, it is possible for change of this address to be detected, and for sequential circuits in the interior to operate so as to perform reading and writing. Since in this manner an SRAM, operates only by being provided with a simple input signal waveform, as compared with a DRAM, therefore it is possible to simplify the structure of the circuitry which generates this type of input signal waveform.
Furthermore, since with an SRAM no refresh is required for maintaining the data which is stored in the memory cells as is the case with a DRAM, therefore, since no refresh is necessary, along with its operation being simple, it also has the merit that the electrical current for maintaining the data in the standby state is small. Owing to these facts, SRAMs are widely used for many applications. However, since generally an SRAM needs six transistors for each memory cell, if a great capacity is anticipated, the chip size becomes undesirably great as compared to a DRAM, and there is also the shortcoming that the price itself inevitably becomes high as compared to a DRAM.
On the other hand, for a DRAM, because the address is divided into two portions, the row address and the column address, which must be supplied separately, because a RAS (row address strobe)/CAS (column address strobe) becomes necessary as a signal for determining the input timings of these addresses, because it is necessary to refresh the memory cells periodically, and the like, therefore the timing control inevitably becomes more complicated as compared with an SRAM, moreover, extra circuitry and so on for refresh control becomes necessary.
Furthermore with a DRAM there is also the problem that, due to the fact that refresh for the memory cells becomes necessary even when there is no access from the outside, the consumption of electrical current becomes undesirably great. However, since the memory cells of a DRAM can be made up from one capacitor and one transistor each, therefore there is no need to increase the chip size, and it is comparatively easy to count upon increase in capacity. Accordingly, if it is a question of manufacturing semiconductor memory devices of the same capacity, a DRAM is cheaper than an SRAM.
By the way, as semiconductor memory devices which are to be employed in portable instruments of which representative types are the portable telephone and the like, up till the present, SRAMs are the main type used. This is because only simple functions have been incorporated in portable telephones up until now and therefore high capacity semiconductor memory devices have not been required until the present, because in comparison with DRAMs the operation of SRAMs is simple as far as the points of timing control and the like are concerned, because SRAMs are well adapted for portable telephones and the like in which it is desired to extend the continuous speech time period and the continuous standby receive time period as much as possible since their standby current is small and therefore their power consumption is low, and the like.
Nevertheless, nowadays, portable telephones which are endowed with very rich functionality are becoming progressively more popular, and functions are being implemented such as sending and receiving electronic mail, or, by accessing various sites, obtaining urban information such as data about restaurants in the vicinity and the like. Moreover, with the most recent portable telephones, functions such as display of simplified contents of home pages accessed on web servers upon the internet are also imminently to be provided, and it is also being assumed that in the near future it will become possible freely to access home pages and the like upon the internet in the same manner as with a current desktop type personal computer.
In order to implement these kinds of functions, it is useless only to perform simple text display as with old style portable telephones, and a graphic display becomes indispensable in order to present diverse multimedia information to the user. For this, the requirement has arisen for large quantities of data which have been received from a public network or the like to be temporarily stored in a semiconductor memory device within a portable telephone. In other words, for semiconductor memory devices which are to be fitted to portable instruments from now on, it is considered that having large capacity like a DRAM is an essential condition. However, since it is an absolute condition for a portable instrument that it should be small in size and light in weight, it is necessary to avoid increase in size and in weight of the instrument as a whole, even while increasing the capacity of the semiconductor memory device.
Although as described above an SRAM is desirable as a semiconductor memory device to be fitted to a portable instrument when the convenience of application and power consumption are considered, a DRAM comes to be desirable when viewed from the aspect of increasing capacity. In other words, it may be the that from now on semiconductor memory devices which employ the individual merits of SRAMs and of DRAMs will be most suitable for application to future portable instruments. As this type of semiconductor memory device, ones which are termed xe2x80x9cpseudo-SRAMsxe2x80x9d have already been contemplated which, while utilizing memory cells which are the same as those employed in DRAMs, have specifications almost identical to those of SRAMs, when seen from the outside.
With a pseudo-SRAM, when supplying the address, it is not necessary to separate it into a row address and a column address as with a DRAM, and furthermore timing signals such as RAS and CAS for implementing this separation are not required either. With a pseudo-SRAM, just as with a general-purpose SRAM, it is acceptable to supply the address only once, and to perform reading/writing by taking in the address internally upon trigger by a chip enable signal which is equivalent to a clock signal for a semiconductor memory device of the clock signal synchronized type.
Of course a pseudo-SRAM is not limited to having absolute compatibility with a general-purpose SRAM; many of them are equipped with refresh control terminals for controlling refresh of the memory cells from the outside, so that it is necessary to control refresh from the exterior of the pseudo-SRAM. In this manner, many pseudo-SRAMs are not so easy to operate as compared with SRAMs, and there is the defect that it becomes necessary to provide extra circuitry for refresh control. Due to this fact, as is introduced below, it has also come to be contemplated to manage without controlling the refresh of a pseudo-SRAM from the outside, and to provide a pseudo-SRAM which is made so that it can be operated with a specification which is exactly the same as that of a general-purpose SRAM. However various defects are present with this type of pseudo-SRAM as well, as will be described below.
First, as a first related art, the semiconductor memory device which has been disclosed in Japanese Unexamined Patent Application, First Publication No. Hei 4-243087 is proposed. With this related art, the pseudo-SRAM itself has no refresh timer, but rather it is arranged for a timer to be provided externally to the pseudo-SRAM. And an OE (output enable) signal is generated exterior to the pseudo-SRAM when an initial access request is made after the refresh time period has elapsed, and it is arranged for the reading or the writing which corresponds to the access request to be performed after performing a refresh according to this OE signal.
However with a structure like that of this first related art there is the problem that the power consumption becomes too great, and which renders application impossible to a low power consumption product like a portable telephone or the like, a premise for which is that it can be used for a long time period upon battery power. That is to say, with the first related art, it is arranged for the pseudo-SRAM to latch the address which has been input from the outside and to operate when the chip enable signal has become valid. However, since with the first related art it is necessary to change the chip enable signal each time the pseudo-SRAM is accessed, accordingly the power consumption becomes undesirably great due to charging and discharging of the bus lines of the chip enable signal which extend upon the circuit board.
Furthermore, with the first related art, when a read request arrives from the exterior of the pseudo-SRAM, reading of the memory cell which corresponds to the read request is performed after first performing refresh. Accordingly, there is the problem that the starting timing of the read operation is undesirably delayed by just the time period which is required for the refresh operation. In other words the address access time periodxe2x80x94which means the time period from the time point at which the address is determined to the time point at which the read data is output (hereinafter termed TAA)xe2x80x94comes to become undesirably long. This problem is generated in the same way in the case of writing. That is to say, there is the problem that it is not possible to start the write operation until after the refresh has been completed, even if, as an illustration, the write enable signal and the write data have been presented at an early timing within the memory cycle.
Next, as a second related art, the semiconductor memory device which has been disclosed in Japanese Patent No. 2529680 (Japanese Unexamined Patent Application, First Publication No. Sho 63-206994) is proposed. With this related art, a structure being disclosed which, just like a conventional pseudo-SRAM, is arranged so as to control refresh from the outside, a structure is also shown which, while incorporating the structure of this pseudo-SRAM, also incorporates further improvements.
With the former structure, an address transition detect signal is generated upon receipt of the fact that an output enable signal has become valid, refresh is performed according to a refresh address which has been generated interior to the pseudo-SRAM, the address transition detect signal is generated for a second time when the output enable signal has become invalid, and refresh is also performed for an external address which is supplied from the outside of the pseudo-SRAM. However, if the output enable signal is generated periodically for each refresh interval, the latter refresh whose object is the external address is not really necessary, and a useless and undesirable waste of electrical power takes place, insofar as refresh is performed for the external address.
On the other hand, with the latter structure, change of the external address is detected and an address transition detect signal is generated, and refresh is performed for a refresh address which has been generated internally to the pseudo-SRAM in response to this address transition detect signal, and after a fixed time period has elapsed thereafter, it is arranged to generate the address transition detect signal for a second time, and normal reading or writing is performed by taking the external address as an object. However, if reading or writing is performed for a second time after refresh is performed, the same undesirable problem arises as was pointed out with regard to the first related art.
Furthermore, with this type of structure, a problem arises when skew has appeared in the external address. That is to say, when skew is present in the external address, a plurality of address transition detect signals are generated due thereto. Due to this, although the initiation of a refresh by the initial address transition detect signal is acceptable, the normal access to the external address, which really should be performed after the refresh has been completed, is initiated by the second and subsequent address transition detect signals. In other words, in this case, the access request to the external address is undesirably performed, irrespective of whether or not refresh is taking place; and this causes the type of problem described below.
The memory cells of a DRAM are generally of the destructive read type, in which, when some word line is activated and reading is performed by the sense amplifier, it is necessary to write the data which was originally stored in all of the memory cells which are connected to this word line back into these memory cells from the sense amplifier. However, if reading or writing has been initiated during refresh as described above, a plurality of word lines are activated at the same time. If this is done, the data of the memory cells which are connected to these word lines comes to be simultaneously reading upon the same one bit line, so that the electrical potential upon the bit line which is generated in correspondence to the data of the memory cells which should be refreshed is no longer correct. Accordingly, when the electrical potential upon this bit line is amplified and write back (refresh) into the memory cells is performed, the data in the memory cells is destroyed.
Next, as a third related art, the semiconductor memory devices which have been disclosed in Japanese Unexamined Patent Application, First Publication No. Sho 61-5495 and in Japanese Unexamined Patent Application, First Publication No. Sho 62-188096 are proposed. The former semiconductor memory device is internally provided with a refresh timer for timing the refresh interval; a refresh start request is generated when a time period equivalent to the refresh interval has elapsed, and, after the amplification upon the bit line pair during the read operation has been completed, the word line is activated and refresh is performed for the refresh address. By doing this, it is possible to manage without controlling the refresh of the memory cell from the exterior of the semiconductor memory device.
Furthermore, the latter semiconductor memory device is one in which the detailed structure of an operation timing control circuit for implementing the former semiconductor memory device is disclosed in concrete terms, and basically it is the same as the former semiconductor memory device. It should be understood that in the third related art, just as with the first related art and the second related art, it is also disclosed to perform reading or writing after performing refresh. In addition, as a fourth related art which resembles the third related art, there has been proposed the semiconductor memory device which is disclosed in Japanese Unexamined Patent Application, First Publication No. Hei 6-36557. This semiconductor memory device, as well, is equipped internally with a timer for refresh, and it is arranged that a refresh start request is generated when a predetermined refresh time period has elapsed, and the refresh is performed after the reading has been completed.
However, as is disclosed in the third related art, a problem occurs as previously pointed out when the reading or the writing is performed after performing the refresh. Of course, with this third related art or fourth related art, it is also disclosed to perform the refresh after performing the reading or the writing. If this structure is adopted, the problem does not arise, as with the first related art or the second related art, that the address access time period TAA becomes great. However, with the third related art or the fourth related art, the question as to at what timing the write enable signal which determines the write timing is provided is not taken into account at all, and there is a possibility that the following type of problem may occur.
That is to say, if a pseudo-SRAM is operated with the same specification as a general-purpose SRAM, the write enable signal and the write data come to be supplied asynchronously with respect to change of the address. Due to this, it is not possible actually to start the write operation into the memory cell until the write enable signal and the write data are both determined, even if the write address is determined. In other words, until the write enable signal and the write data are determined, there is an undesirable empty time period in which no operation can be performed, and only when these are determined do the writing and the refresh come to be performed in sequence. Due to this, when compared with a structure in which the writing is performed after the refresh, as with the first related art or the second related art, there is the defect that the memory cycle becomes longer by the empty time period.
Here, with a pseudo-SRAM like the first related art through the fourth related art, generally the write operation is performed as follows. That is to say, activation of the word line and selection of the memory cell is continued during the write period, and the write operation to the memory cell is started from the time point that the write enable signal is made valid asynchronously, and the write data is actually written in to the memory cell while a predetermined time period (hereinafter termed the time period TDW) elapses from the timing at which this write data is determined. After this the write enable signal is made invalid, and thenceforward, until again a predetermined time period (hereinafter termed the recovery time period TWR) elapses, it is arranged for pre-charging of the bit line for subsequent access to be performed.
With a general-purpose SRAM a recovery time period TWR like the one described above is actually useless, but with a pseudo-SRAM it is not possible for the recovery time period TWR to be brought to zero, since it is necessary to pre-charge the bit lines just like a DRAM, because DRAM memory cells are employed. In this manner, with a pseudo-SRAM, it is necessary to guarantee the provision of the recovery time period TWR, and there is the fault that the start timing of operation for the next address is delayed, as compared with a general-purpose SRAM. Accordingly, although it is desirable to shorten the above described empty time period or recovery time period TWR, there is a problem with regard to implementing this with a structure like the first related art through the fourth related art.
Furthermore, there is also the following problem with a conventional pseudo-DRAM. That is to say, with a general-purpose SRAM or the like, it is often the case that a standby mode is provided in which the power source supply to the internal circuitry is stopped and the power consumption is extremely low. However, since with a pseudo-SRAM the memory cells themselves are the same as those in a DRAM, refresh is always necessary in order to preserve the data which is being stored in the memory cells. Due to this, with a conventional pseudo-SRAM, while it may be that the operation is the same as that for an SRAM, no standby mode such as that employed with a general purpose SRAM is particularly provided.
However, for operating with the same specification as an SRAM, and from the aspect of convenience of use as well, it is desirable to provide a low power consumption mode which is the same as the standby mode of a general-purpose SRAM. Furthermore, since it is anticipated that pseudo-SRAMs from now on will be put to various applications, it is also considered to be extremely beneficial to provide an individually characteristic pseudo-SRAM standby mode which is not present with a conventional SRAM or the like.
The present invention has been conceived in consideration of the above described points, and its objective is to provide a semiconductor memory device which suffers no influence such as the normal reading and write access being delayed due to refresh, with which no inconvenience such as access delay or destruction of the contents of memory cells occurs even in circumstances such as skew being present in the address, with which it is possible to shorten the entire memory cycle by reducing the write time period, and which is operated according to the specification of a general-purpose SRAM and is of enhanced capacity, and whose chip size is small and whose power consumption is low, and which moreover is of low cost. Furthermore, an objective of the present invention is to propose a semiconductor memory device which has a standby mode which is the same as that employed with a general-purpose SRAM, and a unique low power consumption mode which cannot be seen with a conventional semiconductor memory device.
The semiconductor memory device according to the first aspect of the present invention comprises: a memory cell array comprising memory cells which require refresh; an access circuit which performs refresh of the memory cell array after reading or writing for an access address has been performed for the memory cell array; and a control circuit which, after a memory cycle in which a write request and write data presented asynchronously for the access address is input, makes the access circuit perform late writing using the access address and the write data provided in the memory cycle. In other words, with this semiconductor memory device, for writing, late writing is employed which writing is performed after the memory cycle in which the write request was input. Due to this, both of the access address and the write data are determined when late writing is performed, so that it is possible, by using them, to start writing to the memory cell array immediately. Accordingly, no longer does an empty time period occur in the memory cycle because the write data is not determined, as in the related art, and it is possible to shorten the memory cycle. Furthermore, it is possible to perform the operations of writing and refresh, and the operation of taking in the access address and the write data, in parallel. Accordingly, it is not necessary to ensure any recovery time period after writing to the memory cell array as in the related art, so that it is possible to shorten the memory cycle.
With the semiconductor memory device according to the above described first aspect, in a memory cycle in which a next write request for the preceding write request is presented, the control circuit may perform writing corresponding to the preceding write request by late writing. Furthermore, the control circuit may detect that a chip is in the non selected state or the deactivated state, and performs the late writing during the non selected state or the deactivated state. By doing this, it no longer happens that a read request or a new write request is presented while late writing is being performed. Because of this the inconvenience does not occur of a read request or a new write request arriving while late writing is being performed, so that the start of operation with regard to these requests is delayed until the late writing is completed.
The semiconductor memory device according to the second aspect of the present invention is the semiconductor memory device of the above described first aspect, further comprising: an address transition detect circuit which detects whether a chip has transited from the non selected state to the selected state, or that the access address has changed, and wherein the control circuit starts the reading or the writing after a skew period has elapsed which is set greater than or equal to the maximum value of a skew included at least one of a chip select signal which controls the selected state or non selected state, and the access address, taking the time of detection as a reference,
Furthermore, the semiconductor memory device according to the third aspect of the present invention comprises: a memory cell array comprising memory cells which require refresh; an access circuit which performs refresh of the memory cell array after performing reading of the memory cell array for an access address or writing of the memory cell array for the access address based on a write request and write data presented asynchronously for the access address; an address transition detect circuit which detects whether a chip has transited from the non selected state to the selected state, or that the access address has changed; and a control circuit which starts the reading or the writing after a skew period has elapsed which is set greater than or equal to the maximum value of a skew included at least one of a chip select signal which controls the selected or non selected state, and the access address, taking the time of detection as a reference.
According to the semiconductor memory devices according to the above described second and third aspects, it is possible to start the reading or the writing after the skew period has elapsed from when the chip select signal or the access address has changed. Accordingly, it is possible to start the operation for reading or writing immediately when the access address has been determined, so that it is possible to increase the speed of access for reading or writing.
With the semiconductor memory devices according to the above described second and third aspects, the control circuit may set the completion timing of the skew period after the time at which it is determined whether the write request is presented, and may determine within the skew period whether a write request has been presented. By doing this, no longer do the inconveniences occur, as in the related art, that the start of a write operation is delayed and a dummy read operation is started, and the dummy reading is interrupted by the write operation so that the memory cells are destroyed, or that the memory cycle is made longer by the start of a write operation being delayed until a dummy reading is completed.
The semiconductor memory device according to the fourth aspect of the present invention comprises: a memory cell array comprising memory cells which require refresh; an access circuit which performs refresh of the memory cell array after performing reading or writing of the memory cell array for the access address in the same memory cycle; an address transition detect circuit which detects whether a chip has transited from the non selected state to the selected state, or that the access address has changed; and a control circuit which sets a completion timing for a skew period having a length greater than or equal to the maximum value of a skew included at least one of a chip select signal which controls the selected state or non selected state, and the access address, taking the time of detection as a reference, after a write request and write data presented asynchronously for the access address are determined. In this manner, by determining both the write request and the write data for performing writing within the skew period, writing or reading and refresh are performed within the same memory cycle that the write request arrived. Accordingly it is no longer necessary to perform late writing as with the semiconductor memory device according to the first aspect, and it is possible to reduce the scale of the circuit structure and to simplify it by the amount which is gained by not providing the structure which is necessary for late write control.
And, with the semiconductor memory devices according to the above described second through fourth aspects, it is arranged to access the memory cells after the skew period has elapsed from the change of access address. Due to this, it becomes unnecessary to change the chip enable signal or the like every time the address is taken in, as with an existing pseudo-SRAM, so that it is possible to reduce the power consumption to that extent.
With the semiconductor memory devices according to the above described second through fourth aspects, if writing, reading, or refresh which was started in a memory cycle preceding to the current memory cycle in which a read request or a write request occurred has not been completed by the completion timing of a skew period for the current memory cycle, the control circuit delays the start of writing or reading in the current memory cycle until the writing, reading, or refresh has been completed. In other words, if the writing, reading, or refresh which has been started in the previous memory cycle has not been completed by the end of the skew period of the current memory cycle, then it will be acceptable to delay the start of writing or reading of the current memory cycle until these operations are completed. By doing this, it never happens that the writing, reading, or refresh compete mutually with one another even if writing or reading and the refresh following it are not completed within one memory cycle. Accordingly, it becomes possible to anticipate a shortening of the cycle time and an increase in speed of the semiconductor memory device.
With the semiconductor memory devices according to the above described first through fourth aspects, the access circuit may perform reading or late writing simultaneously for a plurality of addresses in the memory cell array, and the control circuit may perform the operation of sequentially outputting to the outside read data which have been obtained by the reading, or the operation of sequentially taking in write data which are input from the outside for the next late writing, in parallel with the refresh. By doing this it is possible to shorten the cycle time, since the refresh period has become invisible when seen from the outside of the semiconductor memory device. In this case, the control circuit may detect a change of predetermined upper bits in the access address, and, when performing the reading or the late writing, successively outputs the read data or successively takes in the write data for a plurality of addresses for which the predetermined upper bits in the access address are the same, while varying the lower address in the access address which is made up from the bits other than the predetermined upper bits.
By doing this, it becomes possible to implement the same functions as the page mode or the burst mode which are employed with a general-purpose DRAM or the like. Furthermore, in this case, the control circuit may successively output the read data or successively take in the write data according to the lower address supplied from the outside. By doing this, it is possible to perform input and output of data while randomly changing the lower address, as with the page mode. Furthermore, in this case, the control circuit may successively output the read data or successively take in the write data while varying the lower address according to a predetermined order based upon an initial value of the lower address supplied from the outside. By doing this, it becomes sufficient to supply only the start address for burst operation to the semiconductor memory device, and it is possible to simplify the structure of the controller or the like which is provided external to the semiconductor memory device.
With the semiconductor memory devices according to the above described first through fourth aspects, there may be further comprised: a refresh control circuit comprising circuitry within the access circuit and the control circuit which performs control of the refresh, and a refresh address generation circuit which generates a refresh address showing memory cells to be refreshed, and which updates the refresh address each time the refresh is performed; a voltage generation circuit which generates voltages supplied to parts within the device; and a mode switching circuit which switches to one of a first mode in which power source is supplied both to the refresh control circuit and to the voltage generation circuit, a second mode in which supply of power source to the refresh control circuit is stopped while power source is supplied to the voltage generation circuit, and a third mode in which supply of power source both to the refresh control circuit and to the voltage generation circuit is stopped, and which controls whether supply of power source is performed to the refresh control circuit and the voltage generation circuit according to the switched mode. Due to this, it is possible finely to control from outside whether it is necessary to keep the data in the standby state, the time period to return to the active state, the amount of consumption of current, and so on, in correspondence to the equipment to which the device is applied and its environment of use and the like. In other words since, in the first mode, power source is supplied to the circuits which are required for refresh, thereby, along with being able to keep the data in the memory cells, it is possible to make the time period until transition from the standby state to the active state to be of the minimum length among the three types of mode. Furthermore, in the second mode, it is possible to reduce the consumption of current lower than in the first mode by the amount which was required to be supplied to the refresh control circuit, also, in the event of transition to the active state from the standby state, and it is possible to use the semiconductor memory device immediately in the same manner as with the first mode, just by initializing the data of the memory cells when transition from the standby state to the active state is performed. Moreover, in the third mode, it is possible to make the current consumption the minimum among the three types of mode. In this case, the mode switching circuit may perform switching of mode by detecting that writing of predetermined data in each mode has been performed for a predetermined address. By doing this it becomes unnecessary to provide a dedicated signal from outside of the semiconductor memory device for switching of standby mode, and furthermore the provision of a pin upon the semiconductor memory device for this type of dedicated signal becomes unnecessary.
The semiconductor memory device according to the fifth aspect of the present invention comprises: a memory cell array comprising memory cells which require refresh; an access circuit which performs refresh of the memory cell array accompanying a write cycle for an access address, and performs refresh of the memory cell array spontaneously after a predetermined time period has elapsed from performing the refresh which accompanies the write cycle; and a control circuit which, after a memory cycle in which a write request and write data presented asynchronously for the access address is input, makes the access circuit performing late writing using the access address and the write data which is provided in the memory cycle.
And, with the semiconductor memory device according to any of the aspects of the present invention, it is possible to anticipate an increase of the speed of access, as compared with the case in which reading or writing is performed after having performed the refresh, since the refresh is performed after the reading or the writing has been performed. In addition to this, with the present invention, it becomes no longer necessary to divide the address into two portions to take it in according to a RAS/CAS timing signal as with a general-purpose DRAM, since it is acceptable to provide the access address all at once, and thus it is possible to simplify the circuit structure for generating the signal waveform which must be input to the semiconductor memory device. Furthermore, since the refresh is performed in a single memory cycle in accompaniment with access from the outside of the semiconductor memory device, if the access requests are present which are necessary for refreshing all the memory cells, then it is possible to continue maintaining the data of the memory cells without performing refresh control from the outside of the semiconductor memory device, and the operation is easy, just as with a general-purpose SRAM. Furthermore, if as with a DRAM a single transistor and a single capacitor are used as components for the memory cell, then, along with a great increase in capacity, it is possible to anticipate a reduction of chip size and a minimization of cost, since it is possible considerably to reduce the cell area in comparison with a general-purpose SRAM which requires six transistors per memory cell.